1. Field of the Invention
The present invention relates generally to compositions for chemical mechanical planarization, particularly to compositions for chemical mechanical planarization of copper, tantalum and tantalum nitride layers as occur in the manufacture of integrated circuits.
2. Description of Related Art
Modern integrated circuits typically comprise millions of active devices on a single substrate, electrically interconnected through the use of single and multilevel interconnections including conductive lines and plugs (“vias”). Conventionally, integrated circuits include a semiconductor substrate and a plurality of sequentially formed dielectric layers and conductive patterns, including conductive lines, vias and interconnects. Typically, the conductive patterns on different layers, i.e. upper and lower layers, are electrically connected by a conductive interconnect or plug filling a via opening through the interlayer dielectric (“ILD”), while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. As is known in the art, a damascene technique can be employed to form interconnects by forming an opening or channel in the ILD and filling the opening with a conductive material, typically a metal. The metal typically fills the channel in the ILD and covers the field region atop the ILD between channels. Planarization typically is the next step, removing the metal in the field region, removing barrier/adhesion layers (if any), and providing a substantially planar surface for further coating and patterning.
A dual damascene technique is also known in the art and can be employed to form conductive plugs and lines simultaneously. Basically, dual damascene involves forming an opening comprising a lower contact or via opening section in communication with an upper channel section, and filling the opening and channel section with a conductive material, typically a metal, to simultaneously form an electrically connected conductive plug and channel combination. Planarization follows, to remove metal and other materials as in the damascene technique.
Elemental aluminum and its alloys have been traditionally employed for filling metallic channels and vias in the fabrication of integrated circuits having relatively low integration density. The advantages of aluminum include its low resistivity, superior adhesion to typical dielectric layers (e. g. SiO2), ease of patterning, and high purity.
However, aluminum and aluminum alloys are susceptible to detrimental increases in contact resistances during high temperature processing. Another problem associated with the use of aluminum and aluminum alloys in integrated circuits is electromigration, which becomes a more serious concern as the level of integration and the density of components increase. The higher number of circuit components in very large-scale integration (“VLSI”), ultra large-scale integration (“ULSI”), and even higher densities, requires the use of conductive interconnects with smaller cross sections. This causes higher electrical resistance in the interconnect and increased heat generation. Accordingly, as integrated circuit patterning schemes continue to miniaturize to submicron dimensions, aluminum based metallurgies have become increasingly marginal for handling the increased circuit speed and current density requirements. Materials having higher conductivity than aluminum or its alloys would be advantageous for use as interconnects. Hence, the escalating requirements for high density and performance associated with VLSI, ULSI and beyond require responsive changes in multilevel interconnection technology.
Currently, copper and copper alloys are receiving considerable attention as replacement materials for, inter alia, aluminum and aluminum alloys in VLSI and ULSI multilevel metallization systems. Copper has a lower resistivity than aluminum, and also significantly higher resistance to electromigration. However, problems with integrating copper metal into multilevel metallization systems include the difficulty of etching copper and its relatively high diffusivity. Since copper is difficult to pattern precisely and economically, damascene or dual damascene processing is typically preferred over subtractive patterning processes for creating copper interconnections. To hinder copper diffusion and to enhance its adhesion, barrier/adhesion layers (typically Ta/TaN) are used to separate the copper interconnections from the surrounding dielectric and to enhance the adhesion of the copper. However, these multicomponent layered structures of Cu/Ta/TaN/ILD exacerbate the problems of providing smooth surfaces for accurate patterning, while accurate patterning is increasingly necessary for providing reliable electrical contact to submicron features.
Chemical Mechanical Planarization (also referred to as Chemical Mechanical Polishing), or CMP, is the process of removing material and forming a substantially planar layer before additional layers are deposited and/or additional patterning occurs. CMP of copper and copper alloys deposited on a tantalum (Ta) and/or tantalum nitride (TaN) barrier/adhesion layer has become the subject of considerable interest. For economy of language, we refer to copper and/or copper alloys as “copper” and barrier/adhesion layer(s) as “barrier layer,” understanding thereby that the copper conductor may include copper alloys (among other materials) and the barrier layer may have adhesive as well as barrier functions.
Slurries previously employed in the CMP processes of copper and/or barrier layers have suffered from several disadvantages, including an inadequate selectivity between removal rates of copper and barrier material. The selectivity in the removal of copper and barrier materials should be neither too high nor too low. Uncontrollable removal rates can be the undesirable result. Over-polishing of some materials in order to remove other materials may also occur when selectivity is too high. Over-polishing can lead to significant degradation, dishing or erosion of the surface being over-polished and consequently poor planarization.
Furthermore, current polishing slurries employed in these CMP processes have suffered from poor within-wafer-nonconformity values. Within-wafer-nonuniformity is a known way to quantify the uniformity of material removal rate on many points over a wafer. For example, pre-CMP thickness measurements are typically taken by measuring forty-nine points on each wafer and then post-CMP thickness measurements are taken at the same points. Within-wafer-nonuniformity is then calculated from the following formula:Within-wafer-nonuniformity (“WIWNU”) %=100[σ(Δi)/ave(Δi)]  Eq. 1.where                Δi=thickness of the material removed from point i on the wafer;        σ(Δi)=standard deviation of all Δi values on the wafer; and        ave(Δi)=mean of all Δi values on the wafer.        
The set of Δi's are equal to the thickness removed or the pre-CMP thickness minus the post-CMP thickness for each of the measured points, i. Typically, good within-wafer-nonuniformity values are less than about 5%.
For the foregoing reasons, among others, there is a need for CMP slurry compositions that, inter alia, planarize or polish copper and/or Ta and/or TaN barrier layers at desirable high polishing rates while minimizing surface imperfections, defects, corrosion, dishing and erosion. Particularly, there is a need for one or more CMP slurry compositions that provide good selectivity between copper and barrier removal rates while providing good within-wafer-nonuniformity values. Additionally, there is a need for one or more CMP slurry compositions that provide a high copper removal rate and a low Ta and/or TaN barrier removal rate while avoiding significant degradation, dishing or erosion. Thus, ideally, there is a need for, inter alia, a “phase-one” or a first chemical mechanical planarization or polishing slurry for use in connection with copper damascene or dual damascene processes that removes the copper from the field region between the copper-containing interconnects and stops planarizing when the barrier layer is reached. We refer to wafers having copper deposited thereon as in a damascene or dual damascene process as “copper wafers,” understanding that excess field region copper is to be removed by the CMP process. Following removal of the field region copper and exposure of the barrier layer in the phase-one CMP process, the barrier layer is then removed to complete the planarization. Different processing conditions and/or different CMP compositions are typically employed for the removal of the barrier layer.
We consider two general classes of CMP processes for the polishing of copper wafers. The first process employs a copper single-step slurry process involving a single chemical composition of the CMP slurry throughout the planarization that removes both the copper and barrier materials. This first CMP process is typically continuous, but polishing steps can be divided into as many sub-steps as needed by varying polishing pressure, speeds and other processing parameters. In general, a CMP processing step employing high polishing pressure can remove copper topography and planarize the surface efficiently with good removal uniformity. Subsequently, a step is employed using lower polishing pressure to remove the remaining copper substantially uniformly and continuing to remove barrier layer (tantalum/tantalum nitride or tungsten (W), among others) with a lower removal rate.
The second general class of CMP processes involves a phase-one and phase-two copper CMP process comprised of two separate polishing steps using two separate polishing slurry compositions. Phase-one slurry (or the first CMP step), typically containing oxidizer and abrasive, is designed to planarize copper topography quickly and then continue to remove the copper metal while maintaining good uniformity to the barrier layer. In the phase-two step, a slurry with an oxidizer is typically used to remove the barrier layer (TaN and/or Ta).
The present invention is directed to a phase-one or a first chemical mechanical planarization or polishing slurry that is able to selectively polish the copper portion of a copper wafer having a tantalum and/or tantalum nitride layer. Embodiments of the present invention include CMP compositions that polish both copper and barrier layers (under different polishing conditions) as well as compositions that polish only copper.